3D記憶體架構國際短期課程

活動說明

三維晶片堆疊(3D die-stacking)為突破摩爾定律限制的一個重大半導體技術創新。運用三維晶片堆疊技術,不同製程的晶片有機會異質整合,傳輸頻寬亦可藉由晶片間高密度的連線而大幅提升。三維堆疊記憶體(Die-stacked Memory)為現今三維堆疊領域最主要的應用之一,固態技術協會(JEDEC)已於2011年底正式發表Wide I/O記憶體標準,未來相關產業將更蓬勃發展。因此我們特別邀請到台灣積體電路製造 (TSMC) 李憲信(Hsien-Hsin S. Lee)博士,及超微半導體(AMD) 樂秀威(Gabriel Loh)博士,帶來為期一天的3D記憶體架構短期課程課程。

李憲信博士的演講將介紹過去三維系統整合的技術發展,介紹台積電所提出符合WideI/O記憶體標準之Chip-on-Wafer-on-Substrate (CoWoS)技術。

Gabriel Loh博士將對三維堆疊記憶體的架構演進做一專題介紹,其內容除技術回顧外,更將針對三維堆疊記憶體產品對於系統架構設計所帶來的衝擊及挑戰進行深入分析。

活動期間

中華民國102年2月21日(四)【共一日】

活動費用及名額

學生免費,教師$500,業界人士$800。共 180 個名額。請於活動當日至報到台繳費。

報名時間

即日起至民國 102 年 2 月 6 日 (三) 止

*因場地有限,如名額已滿將提早結束報名,主辦單位保留審核報名資格之權利*

主辦單位

教育部 / 教育部智慧電子整合性人才培育計畫-高階應用處理器AP聯盟中心

國立台灣大學資訊工程學系

承辦單位

國立交通大學資訊工程學系

國立交通大學電子工程學系

活動議程

 

時間

活動內容

09:00-09:10

報到

09:10-09:20

開幕式致詞

交通大學資訊科學與工程研究系 徐慰中教授

09:20-10:20

第一場

講題:The Quest for a New Dimension of System Integration

主講人:Hsien-Hsin S. Lee 李憲信 教授 (TSMC)

主持人:交通大學資訊科學與工程研究所 徐慰中 教授

10:20-10:30

茶敘

10:30-12:10

第二場

講題:Die Stacking and It Architectural Implications

主講人:Gabriel H. Loh (AMD)

主持人:交通大學資訊工程系 范倫達 副教授

12:10-13:10

午餐/自由交流

13:10-14:50:

第三場

講題:Introduction to Die-Stacked Memory Systems

主講人:Gabriel H. Loh (AMD)

主持人:台灣大學資訊工程系 楊佳玲 教授

14:50-15:10

茶敘

15:10-16:40

第四場

講題:Advanced Topics in Organizing Die-Stacked Memory Systems

主講人:Gabriel H. Loh (AMD)

主持人:台灣大學資訊工程系 楊佳玲 教授

16:40-17:00

Q&A         主持人:台灣大學資訊工程系 楊佳玲 教授

 

備註:本課程為全程英文演說

 


Abstract/Summary:

Session1

While innovation in manufacturing continues to push the envelope of CMOS device scaling toward the physical limit, at the meantime, system integration has found an alternative path to delay the limitation by using silicon-interposer based design with through-silicon-via (TSV) or true 3-D IC die stacking to cram more devices within the same chip package. These solutions enable tight integration of heterogeneous processes, miniaturize the overall footprint of a sub-system, and provide shorter interconnect with higher bandwidth, thereby improving both the power and performance. In this talk, I will describe the evolutionary endeavor to the realization of 3-D IC. I will then discuss the latest Chip-on-Wafer-on-Substrate (CoWoS) technology offered by TSMC and the test vehicle implementation with wide I/O DRAM, followed by my view of the prospect of true 3D die stacking.

Session2-Session4

In the first session of this tutorial, I will provide a brief overview and review of die-stacking technologies, covering some of the different types of options out there for stacking, and in particular focusing on how the different approaches can impact the architecture of future microprocessor designs. Examples from the academic literature will be covered, demonstrating different tradeoffs depending on the aggressiveness of the chosen stacking technology. In the second and third sessions of the tutorial, I will focus on architectural approaches for 3D-stacked memories, as this is one of the first major application areas of die stacking. For all commodity markets that require significant memory capacity and upgradable memory, die-stacked DRAM alone will not be sufficient, which creates technical challenges for the architecture and system organization. I will review a variety of techniques to seamlessly integrate the stacked memory without any software visibility, surveying many recent works from the literature. For the market segments where stacked memory capacities are sufficient, then there are also new opportunities to improve the memory and system design to better exploit the very-high TSV bandwidth.

 


 

Biography:

Hsien-Hsin Sean Lee

Hsien-Hsin Sean Lee is a department manager leading process design kit development of the Design and Technology Platform at TSMC. He is currently on leave from Georgia Tech where he was an associate professor at the School of Electrical and Computer Engineering since 2002. His research interests include computer architecture, low-power microelectronics, and 3-D IC. Prior to academia, he was a senior CPU architect at Intel working on Pentium Pro and Pentium III processor (1995-99) and a research staff member working on Itanium processor (1999-2001). He later became an architecture manager of the StarCore DSP center, a joint venture by Lucent/Agere and Motorola leading their SC-140E development and its proliferation for 3G infrastructure (2001-02). Dr. Lee’s Ph.D. research received the Horace H. Rackham Distinguished Dissertation Award from the University of Michigan. At Georgia Tech, he received the DOE Early CAREER PI Award, the NSF CAREER Award, the Georgia Tech ECE Outstanding Jr. Faculty Award, and an IBM Faculty Award. He has published 2 book chapters and more than 90 technical articles including four papers that won the Best Paper Award (MICRO-33, CASES-04, IBM PAC2’05, ANCS-11), four nominated for the Best paper Award (MIT HPEC-07, FPL-07, ICCAD-09, IEEE TCAD 2010) and one selected in IEEE MICRO Top Picks. He holds four U.S. patents and is a senior member of both the IEEE and the ACM.

Gabriel Loh

Gabriel H. Loh  is a Principal Member of the Technical Staff in AMD Research, the research and advanced development lab for Advanced Micro Devices, Inc.  Gabe received his Ph.D. and M.S. in computer science from Yale University in 2002 and 1999, respectively, and his B.Eng. in electrical engineering from the Cooper Union in 1998.  Gabe was also a tenured associate professor in the College of Computing at the Georgia Institute of Technology, a visiting researcher at Microsoft Research, and a senior researcher at Intel Corporation. His research interests include computer architecture, processor microarchitecture, emerging technologies and 3D die stacking.  He is a senior member of IEEE and the ACM, member of the MICRO “Hall of Fame”, (co-)inventor on over forty US patent applications, and a recipient of the US National Science Foundation Young Faculty CAREER Award.

 

 


 

校內導覽

>> http://guidetour.nctu.edu.tw/ch/ind_01.html交通資訊 

下載高解析度地圖 >> 交大停車場位置導覽圖>> 交大校內地圖
南下 :

中山高速公路新竹交流道(94.5K)下,新竹光復路方向第一個紅 綠燈左轉進入大學路,即可抵達本校北大門。

北上:

(1) 中山高速公路新竹交流道(94.5K)下,往新竹方向,行駛光復路,左轉大學路,即可抵達本校北大門。

(2)中山高速公路新竹交流道(97K)下,左轉園區二路直駛約三分鐘,在園區二路盡頭左轉新安路,即可抵達本校南大門。

客運

搭乘統聯「 板橋–北二高–新竹」線,即可直達本校。

高鐵

高鐵(接駁專車)。高鐵新竹站–交通大學站下車,轉市區2路公車或步行至本校。

公車:

新竹火車站下車,步行至民族路光南對面的新竹客運二路站牌,可搭二路公車直達交大光復校區。

新竹客運二路公車時刻表

國立交通大學交通車

[光復>博愛]及[光復>竹北]交通車時刻總表

備註:本課程為全程英文演說

國立交通大學工程四館國際會議廳 / 新竹市大學路1001號

Event Tickets

Ticket Type Sale Period Price
入場券 2013/01/24 10:00(+0800) ~ 2013/02/06 09:00(+0800) End of Sale
  • Free
Next Step